1. Field of the Invention
This invention generally relates to a semiconductor package structure and a method for manufacturing the same, and more particularly to a wafer level semiconductor package structure and a method for manufacturing the same.
2. Description of the Related Art
The semiconductor package mainly serves four functions, i.e. signal distribution, power distribution, heat dissipation and element protection. In general, a semiconductor chip is packaged into an enclosure, and then disposed on a printed circuit board, together with other components, such as capacitors, resistors, inductors, filters, switches, and optical and RF components.
The complementary metal-oxide semiconductor (CMOS) technology for making optical components is similar to that for making semiconductor chips. CMOS is typically formed from silicon (Si) and germanium (Ge) and generally includes N-type metal-oxide semiconductor (NMOS) transistors with negative charged carriers and P-type metal-oxide semiconductor (PMOS) transistors with positive charged carriers. Such NMOS and PMOS may generate currents after sensing light, and the currents may be then recorded and read as image.
Further, as the demands for lighter and more complex electronic devices gradually increase, the operating speed and the complexity of IC chips have become higher and higher. Accordingly, higher packaging efficiency is required. In the prior art, various semiconductor packages and manufacturing methods have been provided for improving the packaging efficiency and reliability. For example, U.S. Pat. No. 6,040,235 entitled “Methods And Apparatus For Producing Integrated Circuit Devices” issued to Badehi on May 21, 2000, and U.S. Pat. No. 6,117,707 entitled “Methods Of Producing Integrated Circuit Devices” issued to Badehi on Sep. 12, 2000 disclose methods for manufacturing the semiconductor package structures. However, these semiconductor package structures and the manufacturing methods in the prior art still have many limitations and drawbacks, and therefore can not entirely meet the requirements for the semiconductor package structures.
Accordingly, there is a need for providing a wafer level semiconductor package to further meet the requirement on the semiconductor package structure.